 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| (R) SP505 WAN Multi-Mode Serial Transceiver +5V Only Operation Seven (7) Drivers and Seven (7) Receivers Driver and Receiver Tri-state Control Internal Transceiver Termination Resistors for V.11 and V.35 Protocols Loopback Self-Test Mode Software Selectable Protocol Selection Interface Modes Supported: RS-232 (V.28) X.21/RS-422 (V.11) EIA-530 (V.10 & V.11) EIA-530A (V.10 & V.11) RS-449 (V.10 & V.11) V.35 (V.35 & V.28) V.36 (V.10 & V.11) RS-485 (un-terminated V.11) Improved ESD Tolerance for Analog I/Os High Differential Transmission Rates SP505A - 10Mbps SP505B - over 16Mbps Compliant to NET1/2 and TBR2 Physical Layer Requirements (TUV Test Report NET2/052101/98) (TUV Test Report CTR2/052101/98) DESCRIPTION... The SP505 is a monolithic device that supports eight (8) popular serial interface standards for DTE to DCE connectivity. The SP505 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. The SP505 requires no additional external components for compliant operation for all of the eight (8) modes of operation. All necessary termination is integrated within the SP505 and is switchable when V.35 drivers, V.35 receivers, and V.11 receivers are used. The SP505 can operate as either a DTE or DCE. Additional features with the SP505 include internal loopback that can be initiated in either single-ended or differential modes. While in loopback mode, driver outputs are internally connected to receiver inputs creating an internal signal path convenient for diagnostic testing. This eliminates the need for an external loopback plug. The SP505 also includes a latch enable pin with the driver and receiver address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit word into the address decoder. Seven (7) drivers and one (1) receiver in the SP505 include separate enable pins for added convenience. The SP505 is ideal for WAN serial ports in networking equipment such as routers, switches, DSU/CSU's, and other access devices. V.35 EIA-530 WAN Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCC............................................................................+7V Input Voltages: Logic...............................-0.3V to (VCC+0.5V) Drivers............................-0.3V to (VCC+0.5V) Receivers........................................15.5V Output Voltages: Logic................................-0.3V to (VCC+0.5V) Drivers................................................15V Receivers........................-0.3V to (VCC+0.5V) Storage Temperature..........................-65C to +150C Power Dissipation.........................................2000mW Package Derating: oJA....................................................46 C/W oJC...................................................16 C/W STORAGE CONSIDERATIONS Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125C in order remove moisture prior to soldering. Sipex ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. SPECIFICATIONS TA = +25C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. 0.8 UNITS Volts Volts Volts Volts CONDITIONS LOGIC INPUTS VIL VIH 2.0 0.4 2.4 LOGIC OUTPUTS VOL VOH IOUT= -3.2mA IOUT= 1.0mA V.28 DRIVER DC Parameters Outputs Open Circuit Voltage Loaded Voltage Short-Circuit Current Power-Off Impedance AC Parameters Outputs Transition Time Instantaneous Slew Rate Propagation Delay tPHL tPLH Max.Transmission Rate +15 +15 +100 Volts Volts mA s V/s s s kbps per Figure 1 per Figure 2 per Figure 4 per Figure 5 VCC = +5V for AC parameters per Figure 6; +3V to -3V per Figure 3 +5.0 300 1.5 30 0.5 0.5 120 1 1 230 5 5 V.28 RECEIVER DC Parameters Inputs Input Impedance Open-Circuit Bias HIGH Threshold LOW Threshold AC Parameters Propagation Delay tPHL tPLH Rev. 7/9/03 3 0.8 50 50 1.7 1.2 100 100 7 +2.0 3.0 k Volts Volts Volts ns ns per Figure 7 per Figure 8 VCC = +5V for AC parameters 500 500 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 2 SPECIFICATIONS TA = +25C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER (continued) AC Parameters (cont.) Max.Transmission Rate 120 230 kbps V.10 DRIVER DC Parameters Outputs Open Circuit Voltage Test-Terminated Voltage Short-Circuit Current Power-Off Current AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Max.Transmission Rate +4.0 0.9VOC +6.0 +150 +100 200 50 50 120 100 100 500 500 Volts Volts mA A ns ns ns kbps per Figure 9 per Figure 10 per Figure 11 per Figure 12 VCC = +5V for AC parameters per Figure 13; 10% to 90% V.10 RECEIVER DC Parameters Inputs Input Current Input Impedance Sensitivity AC Parameters Propagation Delay tPHL tPLH Max.Transmission Rate -3.25 4 +3.25 +0.3 50 50 120 120 120 250 250 mA k Volts ns ns kbps per Figures 14 and 15 VCC = +5V for AC parameters V.11 DRIVER DC Parameters Outputs Open Circuit Voltage Test Terminated Voltage Balance Offset Short-Circuit Current Power-Off Current AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate SP505ACF SP505BCF +5.0 +2.0 0.5VOC 0.67VOC +0.4 +3.0 +150 +100 20 50 50 10 16.4 85 85 10 12 18 110 110 20 Volts Volts Volts Volts Volts mA A ns ns ns ns Mbps Mbps per Figure 16 per Figure 17 per Figure 17 per Figure 17 per Figure 18 per Figure 19 VCC = +5V for AC parameters per Figures 21 and 36; 10% to 90% per Figures 33 and 36, CL = 50pF per Figures 33 and 36, CL = 50pF per Figures 33 and 36, CL = 50pF per Figure 33, CL = 50pF fIN = 5MHz fIN = 8.2MHz V.11 RECEIVER DC Parameters Inputs Common Mode Range Sensitivity -7 +7 +0.3 Volts Volts Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 3 SPECIFICATIONS TA = +25C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.11 RECEIVER (continued) DC Parameters (cont.) Input Current Current w/ 100 Termination Input Impedance AC Parameters Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate SP505ACF SP505BCF -3.25 4 80 80 10 16.4 110 110 20 12 18 130 130 +3.25 +60.75 mA mA k ns ns ns Mbps Mbps per Figure 20 and 22 per Figure 23 and 24 VCC = +5V for AC parameters per Figures 33 and 38; CL = 50pF per Figures 33 and 38; CL = 50pF per Figure 33; CL = 50pF per Figure 33; CL = 50pF fIN = 5MHz fIN = 8.2MHz V.35 DRIVER DC Parameters Outputs Open Circuit Voltage Test Terminated Voltage Offset Source Impedance Short-Circuit Impedance AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate SP505ACF SP505BCF +1.20 +0.66 +0.6 150 165 30 50 50 10 16.4 90 90 20 12 18 40 110 110 30 Volts Volts Volts ns ns ns ns Mbps Mbps per Figure 16 per Figure 25 per Figure 25 per Figure 27; ZS = V2/V1 x 50 per Figure 28 VCC = +5V for AC parameters per Figure 29; 10% to 90% per Figures 33 and 36; CL = 20pF per Figures 33 and 36; CL = 20pF per Figures 33 and 36; CL = 20pF per Figure 33; CL = 20pF fIN = 5MHz fIN = 8.2MHz +0.44 50 135 V.35 RECEIVER DC Parameters Inputs Sensitivity Source Impedance Short-Circuit Impedance AC Parameters Propagation Delay tPHL tPLH Differential Skew Max.Transmission Rate SP505ACF SP505BCF Driver Output 3-State Current Rcvr Output 3-State Current +80 90 135 80 80 10 16.4 110 110 20 12 18 100 1 500 10 110 165 130 130 mV ns ns ns Mbps Mbps A A per Figure 30; ZS = V2/V1 x 50 per Figure 31 VCC = +5V for AC parameters per Figures 33 and 38; CL = 20pF per Figures 33 and 38; CL = 20pF per Figure 33; CL = 20pF per Figure 33; CL = 20pF fIN = 5MHz fIN = 8.2MHz per Figure 32; Drivers disabled DECX = 0000, 0.4V VO 2.4V TRANSCEIVER LEAKAGE CURRENTS Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 4 OTHER AC CHARACTERISTICS TA = +25C and VCC = +5.0V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.70 5.0 s tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 0.40 0.20 0.40 2.0 2.0 2.0 s s s CONDITIONS CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S1 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 15pF, Fig. 34 & 37; S1 closed CL = 15pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 15pF, Fig. 34 & 37; S1 closed CL = 15pF, Fig. 34 & 37; S2 closed 0.15 0.20 0.20 0.15 2.0 2.0 2.0 2.0 s s s s 2.80 0.10 0.10 0.10 10.0 2.0 2.0 2.0 s s s s 2.60 0.10 0.10 0.15 10.0 2.0 2.0 2.0 s s s s RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.12 2.0 s CL = 100pF, Fig. 35 & 38; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 s CL = 100pF, Fig. 35 & 38; S2 closed Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 5 OTHER AC CHARACTERISTICS (Continued) TA = +25C and VCC = +5.0V unless otherwise noted. PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state MIN. TYP. 0.10 0.10 0.10 0.10 MAX. 2.0 2.0 2.0 2.0 UNITS s s s s CONDITIONS CL = 100pF, Fig. 35 & 39; S1 closed CL = 100pF, Fig. 35 & 39; S2 closed CL = 15pF, Fig. 35 & 39; S1 closed CL = 15pF, Fig. 35 & 39; S2 closed CL = 100pF, Fig. 35 & 39; S1 closed CL = 100pF, Fig. 35 & 39; S2 closed CL = 15pF, Fig. 35 & 39; S1 closed CL = 15pF, Fig. 35 & 39; S2 closed 0.10 0.10 0.10 0.10 2.0 2.0 2.0 2.0 s s s s TRANSCEIVER TO TRANSCEIVER SKEW V.28 Driver 100 100 V.28 Receiver 20 20 V.11 Driver 2 2 V.11 Receiver 3 3 V.10 Driver 5 5 V.10 Receiver 5 5 V.35 Driver V.35 Receiver 4 4 6 6 (per Figures 33, 36, 38) ns | (tphl )Tx1 - (tphl )Tx6,7 | ns | (tplh )Tx1 - (tplh )Tx6,7 | ns | (tphl )Rx1 - (tphl )Rx2,7 | ns | (tphl )Rx1 - (tphl )Rx2,7 | ns | (tphl )Tx1 - (tphl )Tx6,7 | ns | (tplh )Tx1 - (tplh )Tx6,7 | ns | (tphl )Rx1 - (tphl )Rx2,7 | ns | (tphl )Rx1 - (tphl )Rx2,7 | ns | (tphl )Tx2 - (tphl )Tx3,4,5 | ns | (tplh )Tx2 - (tplh )Tx3,4,5 | ns | (tphl )Rx2 - (tphl )Rx3,4,5 | ns | (tphl )Rx2 - (tphl )Rx3,4,5 | ns ns ns ns | (tphl )Tx1 - (tphl )Tx6,7 | | (tplh )Tx1 - (tplh )Tx6,7 | | (tphl )Rx1 - (tphl )Rx2,7 | | (tphl )Rx1 - (tphl )Rx2,7 | POWER REQUIREMENTS PARAMETER VCC ICC (No Mode Selected) (V.28/RS-232) (V.11/RS-422) (RS-449) (V.35) EIA-530 EIA-530A V.36 MIN. 4.75 TYP. 5.00 30 60 300 250 105 260 250 65 MAX. 5.25 UNITS Volts mA mA mA mA mA mA mA mA All ICC values are with VCC = +5V, T = +25oC, all drivers are loaded to their specified maximum load and all drivers are active at their maximum specified data transmission rates. CONDITIONS Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 6 TEST CIRCUITS... A A VOC 3k VT C C Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A 7k VT Oscilloscope Isc C Scope used for slew rate measurement. C Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current VCC = 0V A A Ix 3k 2V 2500pF Oscilloscope C C Figure 5. V.28 Driver Output Power-Off Impedance Figure 6. V.28 Driver Output Rise/Fall Times Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 7 A Iia 15V A Voc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3.9k VOC 450 Vt C C Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage VCC = 0V A A Ix Isc 0.25V C C Figure 11. V.10 Driver Output Short-Circuit Current Figure 12. V.10 Driver Output Power-Off Current Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 8 A A Iia 10V 450 Oscilloscope C C Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current V.10 RECEIVER +3.25mA A VOCA 3.9k VOC VOCB -10V -3V B +3V +10V C Maximum Input Current versus Voltage -3.25mA Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 and V.35 Driver Output Open-Circuit Voltage A A Isa 50 VT 50 Isb B VOS B C C Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 9 VCC = 0V A A Ixa 10V 0.25V Iia B B C C VCC = 0V A A 0.25V 10V Ixb B Iib B C C Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current V.11 RECEIVER A +3.25mA 50 Oscilloscope 50 -10V 50 VE -3V +3V +10V B C Maximum Input Current versus Voltage -3.25mA Figure 21. V.11 Driver Output Rise/Fall Time Figure 22. V.11 Receiver Input IV Graph Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 10 V.11 RECEIVER A Iia 6V w/ Optional Cable Termination (100 to 150) i [mA] = V [V] / 0.1 i [mA] = (V [V] - 3) / 4.0 -6V -3V +3V +6V 100 to 150 B i [mA] = (V [V] - 3) / 4.0 C i [mA] = V [V] / 0.1 Maximum Input Current versus Voltage Figure 24. V.11 Receiver Input Graph w/ Termination A A 6V 50 VT 50 100 to 150 Iib B B VOS C C Figure 23. V.11 Receiver Input Current w/ Termination Figure 25. V.35 Driver Output Test Terminated Voltage V1 A A 50 50 VT 50 VOS 24kHz, 550mVp-p Sine Wave V2 B B C C Figure 26. V.35 Driver Output Offset Voltage Figure 27. V.35 Driver Output Source Impedance Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 11 A A 50 Oscilloscope B ISC 50 B 2V 50 C C Figure 28. V.35 Driver Output Short-Circuit Impedance Figure 29. V.35 Driver Output Rise/Fall Time A V1 A 50 24kHz, 550mVp-p Sine Wave V2 B Isc B 2V C C Figure 30. V.35 Receiver Input Source Impedance Figure 31. V.35 Receiver Input Short-Circuit Impedance Any one of the two conditions for disabling the driver. VCC = +5V 0 0 0 0 DEC3 DEC2 DEC1 DEC0 A IZSC 15V CL1 TIN A B CL2 fIN (50% Duty Cycle, 2.5VP-P) VCC A ROUT B 15pF Logic "1" B Figure 32. Driver Output Leakage Current Test Figure 33. Driver/Receiver Timing Test Circuit Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 12 Output Under Test 500 CL S1 VCC Receiver Output CRL Test Point S1 1K S2 1K VCC S2 Figure 34. Driver Timing Test Load Circuit Figure 35. Receiver Timing Test Load Circuit f > 5MHz; tR < 10ns; tF < 10ns DRIVER INPUT +3V 1.5V 0V B A tDPLH VO+ 0V VO- tDPHL VO 1/2VO tPLH tPHL 1/2VO 1.5V DRIVER OUTPUT DIFFERENTIAL OUTPUT VA - VB tR tF tSKEW = | tDPLH - tDPHL | Figure 36. Driver Propagation Delays TXENABLE +3V DECX A, B VOL VOH A, B 0V 0V 5V f = 1MHz; tR 10ns; tF 10ns 1.5V tZL 2.3V Output normally LOW 1.5V tLZ 0.5V 0.5V tHZ 2.3V tZH Output normally HIGH Figure 37. Driver Enable and Disable Times f > 5MHz; tR < 10ns; tF < 10ns V0D2+ A-B V0D2- VOH RECEIVER OUT VOL tSKEW = | tPHL - tPLH | tPLH (VOH - VOL)/2 tPHL 0V INPUT OUTPUT (VOH - VOL)/2 0V Figure 38. Receiver Propagation Delays Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 13 DECX +3V RCVRENABLE 0V f = 1MHz; tR 10ns; tF 10ns 1.5V tZL 1.5V Output normally LOW 1.5V tLZ 0.5V 0.5V tHZ 5V RECEIVER OUT VIL VIH RECEIVER OUT 0V 1.5V tZH Output normally HIGH Figure 39. Receiver Enable and Disable Times +3V DECX or Tx_Enable 0V 0V TOUT VOL f = 60kHz; tR < 10ns; tF < 10ns 1.5V tZL VOL - .5V Output LOW 1.5V tLZ VOL - .5V +3V DECX or Tx_Enable 0V VOH TOUT 0V f = 60kHz; tR < 10ns; tF < 10ns 1.5V tZH VOH - .5V Output HIGH 1.5V tHZ VOH - .5V Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 14 - 0V INPUT - 0V - 0V OUTPUT - 0V Figure 41. Typical V.28 Driver Output Waveform Figure 42. Typical V.10 Driver Output Waveform - 0V INPUT - 0V AOUT BOUT - 0V - 0V DIFFOUT Figure 43. Typical V.11 Driver Output Waveform Figure 44. Typical V.35 Driver Output Waveform Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 15 PINOUT... Pin 61 -- SD(a) -- Analog Out -- Send data, inverted; sourced from TxD. 77 SCT(b) 76 SCT(a) 69 DM(b) 68 DM(a) 71 RD(b) 70 RD(a) 67 CS(b) 66 CS(a) 62 VCC 61 SD(a) 65 TT(b) 63 TT(a) 75 GND 72 GND 64 GND 78 DSR 80 CTS 79 SCT 74 VCC 73 VCC Pin 63 -- TT(a) -- Analog Out -- Terminal Timing, inverted; sourced from TxC Pin 65 -- TT(b) -- Analog Out -- Terminal Timing, non-inverted; sourced from TxC. Pin 70 -- RD(a) -- Receive Data, analog input; inverted; source for RxD. Pin 71 -- RD(b) -- Receive Data; analog input; non-inverted; source for RxD. Pin 76 -- SCT(a) -- Serial Clock Transmit; analog input, inverted; source for SCT. Pin 77 -- SCT(b) -- Serial Clock Transmit: analog input, non-inverted; source for SCT Pin 79 -- SCT -- Serial Clock Transmit; TTL output; sources from SCT(a) and SCT(b) inputs. RxD 1 SDEN 2 TREN 3 RSEN 4 LLEN 5 TTEN 6 SCTEN 7 LATCH 8 DEC3 9 DEC2 10 DEC1 11 DEC0 12 DTR 13 TxD 14 TxC 15 RTS 16 RL 17 RLEN 18 DCD 19 RxC 20 60 GND 59 SD(b) 58 TR(a) 57 GND 56 TR(b) 55 VCC 54 RS(a) 53 GND 52 RS(b) 51 LL(a) SP505 50 GND 49 LL(b) 48 VCC 47 RL(a) 46 GND 45 RL(b) 44 ST(b) 43 GND 42 ST(a) 41 VCC VCC 25 C1+ 26 VDD 27 C2+ 28 VSS 32 VCC 33 RT(a) 37 RT(b) 38 IC(a) 39 STEN 23 GND 29 C1- 30 C - 31 GND 34 RR(a) 35 PIN ASSIGNMENTS... CLOCK AND DATA GROUP Pin 1 -- RxD -- Receive Data; TTL output, sourced from RD(a) and RD(b) inputs. Pin 14 -- TxD -- TTL input ; transmit data source for SD(a) and SD(b) outputs. Pin 15 -- TxC -- Transmit Clock; TTL input for TT driver outputs. Pin 20 -- RxC -- Receive Clock; TTL output sourced from RT(a) and RT(b) inputs. Pin 22 -- ST -- Send Timing; TTL input; source for ST(a) and ST(b) outputs. Pin 37 -- RT(a) -- Receive Timing; analog input, inverted; source for RxC. Pin 38 -- RT(b) -- Receive Timing; analog input, non-inverted; source for RxC. Pin 42 -- ST(a) -- Send Timing; analog output, inverted; sourced from ST. Pin 44 -- ST(b) -- Send Timing; analog output, non-inverted; sourced from ST. Pin 59 -- SD(b) -- Analog Out -- Send data, non-inverted; sourced from TxD. RR(b) 36 IC(b) 40 ST 22 RI 21 LL 24 2 CONTROL LINE GROUP Pin 13 -- DTR -- Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs. Pin 16 -- RTS -- Ready To Send; TTL input; source for RS(a) and RS(b) outputs. Pin 17 -- RL -- Remote Loopback; TTL input; source for RL(a) and RL(b) outputs. Pin 19 -- DCD-- Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs. Pin 21 -- RI -- Ring In; TTL output; sourced from IC(a) and IC(b) inputs. Pin 24 -- LL -- Local Loopback; TTL input; source for LL(a) and LL(b) outputs. Pin 35 -- RR(a)-- Receiver Ready; analog input, inverted; source for DCD. Pin 36 -- RR(b)-- Receiver Ready; analog input, non-inverted; source for DCD. Pin 39 -- IC(a)-- Incoming Call; analog input, inverted; source for RI. Pin 40 -- IC(b)-- Incoming Call; analog input,non-inverted; source for RI. Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 16 Pin 45 -- RL(b) -- Remote Loopback; analog output, non-inverted; sourced from RL. Pin 47 -- RL(a) -- Remote Loopback; analog output inverted; sourced from RL. Pin 49-- LL(b) -- Local Loopback; analog output, non-inverted; sourced from LL. Pin 51 -- LL(a) -- Local Loopback; analog output, inverted; sourced from LL. Pin 52 -- RS(b) -- Ready To Send; analog output, non-inverted; sourced from RTS. Pin 54 -- RS(a) -- Ready To Send; analog output, inverted; sourced from RTS. Pin 56 -- TR(b) -- Terminal Ready; analog output, non-inverted; sourced from DTR. Pin 58 -- TR(a) -- Terminal Ready; analog output, inverted; sourced from DTR. Pin 66 -- CS(a)-- Clear To Send; analog input, inverted; source for CTS. Pin 67 -- CS(b)-- Clear To Send; analog input, non-inverted; source for CTS. Pin 68 -- DM(a)-- Data Mode; analog input, inverted; source for DSR. Pin 69 -- DM(b)-- Data Mode; analog input, non-inverted; source for DSR Pin 78 -- DSR-- Data Set Ready; TTL output; sourced from DM(a), DM(b) inputs. Pin 80 -- CTS-- Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs. Pin 7 -- SCTEN -- Enables SCT receiver; active high; TTL input. Pin 8 -- LATCH -- Latch control for decoder bits (pins 9-12), active low. Logic high input will make decoder transparent. Pins 12-9 -- DEC0 - DEC3 -- Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs. Pin 18 -- RLEN -- Enables RL driver; active low; TTL input. Pin 23 -- STEN -- Enables ST driver; active low; TTL input. POWER SUPPLIES Pins 25, 33, 41, 48, 55, 62, 73, 74 -- VCC -- +5V input. Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 -- GND -- Ground. Pin 27 -- VDD +10V Charge Pump Capacitor -- Connects from VDD to VCC. Suggested capacitor size is 22F, 16V. Pin 32 -- VSS -10V Charge Pump Capacitor -- Connects from ground to VSS. Suggested capacitor size is 22F, 16V. Pins 26 and 30 -- C1+ and C1- -- Charge Pump Capacitor -- Connects from C1+ to C1-. Suggested capacitor size is 22F, 16V. Pins 28 and 31 -- C2+ and C2- -- Charge Pump Capacitor -- Connects from C2+ to C2-. Suggested capacitor size is 22F, 16V. CONTROL REGISTERS Pins 2 -- SDEN -- Enables TxD driver, active low; TTL input. Pins 3 -- TREN -- Enables DTR driver, active low; TTL input. Pins 4 -- RSEN -- Enables RTS driver, active low; TTL input. Pins 5 -- LLEN -- Enables LL driver, active low; TTL input. Pin 6 -- TTEN -- Enables TT driver, active low; TTL input. Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 17 FEATURES... The SP505 is a highly integrated serial transceiver that allows software control of its interface modes. Similar to the SP504, the SP505 offers the same hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS485, V.35, EIA-530 and includes V.36 and EIA530A. The interface mode selection is done via a 4-bit switch for the drivers and receivers. The SP505 is fabricated using low-power BiCMOS process technology, and incorporates a Sipex- patented (5,306,954) charge pump allowing +5V only operation. Each device is packaged in an 80-pin JEDEC Quad FlatPack package. The SP505 is ideally suited for wide area network connectivity based on the interface modes offered and the driver and receiver configurations. The SP505 has seven (7) independent drivers and seven (7) independent receivers. In V.35 mode, the SP505 includes the necessary components and termination resistors internal within the device for compliant V.35 operation. THEORY OF OPERATION The SP505 is made up of five separate circuit blocks -- the charge pump, drivers, receivers, decoder and switching array. Each of these circuit blocks is described in more detail below. Charge-Pump The SP505 charge pump is based on the SP504 design where Sipex's patented charge pump design (5,306,954) uses a four-phase voltage shifting technique to attain symmetrical 10V power supplies. The charge pump still requires external capacitors to store the charge. In addition the SP504 charge pump supplies +10V or +5V on VSS and VDD depending on the mode of operation. There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. The SP505 charge pump is used for RS-232 where the output voltage swing is typically +10V and also used for RS-423. However, RS423 requires the voltage swing on the driver output be between +4V to +6V during an opencircuit (no load). The charge pump would need to be regulated down from +10V to +5V. A typical +10V charge pump would require external clamping such as 5V zener diodes on VDD and VSS to ground. The +5V output has symmetrical levels as in the +10V output. The +5V is used in the following modes where RS423 (V.10) are used: RS-449, EIA-530, EIA530A and V.36. Phase 1 (10V) -- VSS charge storage -- During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to +5V. Cl+ is then switched to ground and the charge on C1- is transferred to C2-. Since C2+ is connected to +5V, the voltage potential across capacitor C2 is now 10V. Phase 1 (5V) -- VSS & VDD charge storage and transfer -- With the C1 and C2 capacitors initially charged to +5V, Cl+ is then switched to ground and the charge on C1- is transferred to the VSS storage capacitor. Simultaneously the C2- is switched to ground and 5V charge on C2+ is transferred to the VDD storage capacitor. VCC = +5V +5V C1 + - C4 + - C2 -5V + - VDD Storage Capacitor - + VSS Storage Capacitor -5V C3 Figure 45. Charge Pump Phase 1 for +10V. VCC = +5V +5V C1 + - C4 + - C2 + - VDD Storage Capacitor -5V - + VSS Storage Capacitor C3 Figure 46. Charge Pump Phase 1 for +5V. Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 18 Phase 2 (10V) -- VSS transfer -- Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to ground, and transfers the generated -l0V or the generated -5V to C3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the negative side is connected to ground. Phase 2 (5V) -- VSS & VDD charge storage -- C1+ is reconnected to VCC to recharge the C1 capacitor. C2+ is switched to ground and C2- is connected to C3. The 5V charge from Phase 1 is now transferred to the VSS storage capacitor. VSS receives a continuous charge from either C1 or C2. With the C1 capacitor charged to 5V, the cycle begins again. Phase 3 -- VDD charge storage -- The third phase of the clock is identical to the first phase -- the charge transferred in C1 produces -5V in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at +5V, the voltage potential across C2 is l0V. For the 5V output, C2+ is connected to ground so that the potential on C2 is only +5V. Phase 4 -- VDD transfer -- The fourth phase of the clock connects the negative terminal of C2 to ground and transfers the generated l0V or the generated 5V across C2 to C4, the VDD storage capacitor. Again, simultaneously with this, the positive side of capacitor C1 is switched to +5V and the negative side is connected to ground, and the cycle begins again. Since both VDD and VSS are separately generated from VCC in a no-load condition, VDD and VSS will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 15kHz. The external capacitors must be a minimum of 22F with a 16V breakdown rating. External Power Supplies For applications that do not require +5V only, external supplies can be applied at the V+ and V- pins. The value of the external supply voltages must be no greater than +l0.5V. The tolerance should be +5% from +10V. The current drain for the supplies is used for RS-232 and RS423 drivers. For the RS-232 driver, the current requirement will be 3.5mA per driver. The RS423 driver worst case current drain will be 11mA per driver. Power sequencing is required for the SP505. The supplies must be sequenced accordingly: +10V, +5V and -10V. It is important to prevent VSS from starting up before VCC or VDD. VCC = +5V C4 + - C1 + - C2 + - VDD Storage Capacitor -10V - + VSS Storage Capacitor C3 Figure 47. Charge Pump Phase 2 for +10V. VCC = +5V C4 + - C1 + - C2 + - VDD Storage Capacitor -5V - + VSS Storage Capacitor C3 Figure 48. Charge Pump Phase 2 for +5V. VCC = +5V +5V C1 + - C4 + - C2 -5V + - VDD Storage Capacitor - + VSS Storage Capacitor -5V C3 Figure 49. Charge Pump Phase 3. VCC = +5V +10V C1 + - C4 + - C2 + - VDD Storage Capacitor - + VSS Storage Capacitor C3 Figure 50. Charge Pump Phase 4. Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 19 Drivers The SP505 has seven (7) enhanced independent drivers. Control for the mode selection is done via a four-bit control word. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. Table 1 shows the mode of each driver in the different interface modes that can be selected. There are four basic types of driver circuits -- V.28, V.11, V.10 and V.35. V.28 Drivers The V.28 drivers output single-ended signals with a minimum of +5V (with 3k & 2500pF loading), and can operate to at least 120kbps under full load. Since the SP505 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 drivers are used in RS-232 mode for all signals, and also in V.35 mode where four (4) drivers are used as the control line signals (DTR, RTS, LL, and RL). V.10 Drivers The V.10 (RS-423) drivers are also single- ended signals which produce open circuit VOL and VOH measurements of +4.0V to +6.0V. When terminated with a 450 load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category II signals from each of their corresponding specifications. V.11 Drivers The third type of driver is a V.11 (RS-422) type differential driver. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain typically +2.2V differential output levels with a load of 100. The signal levels and drive capability of these drivers allow the drivers to also support RS-485 Rev. 7/9/03 requirements of 1.5V minimum differential output levels with a 54 load. The driver is designed to operate over a common mode range of +12V to -7V, which follows the RS-485 specification. This also covers the +7V to -7V common mode range for V.11 (RS-422) requirements. The V.11 drivers are used in RS449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data signals. V.35 Drivers The fourth type of driver is the V.35 driver. These drivers were specifically designed to comply with the requirements of V.35. Unique to the industry, the Sipex's V.35 driver architecture used in the SP505 does not need external termination resistors to operate and comply with V.35. This simplifies existing V.35 implementations that use external termination schemes. The V.35 drivers can produce +0.55V driver output signals with minimum deviation (maximum 20%) given an equivalent load of 100. With the help of internal resistor networks, the drivers achieve the 50 to 150 source impedance and the 135 to 165 short-circuit impedance for V.35. The V.35 driver is disabled and transparent when the decoder is in all other modes. All of the differential drivers; V.11 (RS422) and V.35, can operate over 10Mbps. Driver Enable and Input All the drivers in the SP505 contain individual enable lines which can tri-state the driver outputs when a logic "1" is applied. This simplifies half-duplex configurations for some applications and also provides simpler DTE/DCE flexibility with one integrated circuit. The driver inputs are both TTL or CMOS compatible. Each driver input should have a pull-down or pull-up resistor so that the output will be at a defined state. Unused driver inputs should not be left floating. Receivers The SP505 has seven (7) independent receivers which can be programmed for the different interface modes. Control for the mode selection is done via a 4-bit control word, which is the same as the driver's 4-bit control word. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous (c) Copyright 2003 Sipex Corporation SP505 Multi-Mode Serial Transceiver 20 serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line receivers. Table 2 shows the mode of each receiver in the different interface modes that can be selected. There are three basic types of receiver circuits -- V.28, V.10, and V.11. V.28 Receivers The V.28 receiver is single-ended and accepts V.28 signals from the V.28 driver. The V.28 receiver has an operating voltage range of +15V and can receive signals down to +3V. The input sensitivity complies with RS-232 and V.28 specifications at +3V. The input impedance is 3k to 7k in accordance to RS-232 and V.28 over a +15V input range. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic "1" and a +0.8V maximum for a logic "0". V.28 receivers are used in RS-232 mode for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The V.28 receivers can operate to at least 120kbps. V.10 Receivers The V.10 receivers are also single-ended as with the V.28 receivers but have an input threshold as low as +200mV. The input impedance is guaranteed to be greater than 4K, with an operating voltage range of +7V. The V.10 receivers can operate to at least 120kbps. V.10 receivers are used in RS-449, EIA-530, EIA530A and V.36 modes as Category II signals as indicated by their corresponding specifications. V.11 Receivers The third type of receiver is a differential which supports V.11 and RS-485 signals. This receiver has a typical input impedance of 10k and a typical differential threshold of +200mV, which complies with the V.11 specification. Since the characteristics of the V.11 receivers are actually subsets of RS-485, the V.11 receivers can accept RS-485 signals. However, these receivers cannot support 32-transceivers on the signal bus due to the lower input impedance as specified in the RS-485 specification. Three receivers (RxD, RxC, and SCT) include a typical 120 cable termination resistor across the A and B inputs. The resistor for the three receivers Rev. 7/9/03 is switched on when the SP505 is configured in a mode which uses V.11 receivers. The V.11 cable termination resistor is switched off when the receiver is disabled or in another operating mode not using V.11 receivers. The V.11 receivers are used in X.21, RS-449, EIA-530, EIA-530A and V.36 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential receivers can receive signals over 10Mbps. V.35 Receiver The V.11 receivers are also used for the V.35 mode. Unlike the older implementations of differential receivers used for V.35, the SP505 contains an internal resistor termination network that ensures a V.35 input impedance of 100 (+10) and a short-circuit impedance of 150 (+15). The traditional V.35 implementations required external termination resistors to achieve the proper V.35 impedances. The internal network is connected via low on-resistance FET switches when the decoder is changed to V.35 mode. These FET switches can accept input signals of up to +15V without any forward biasing and other parasitic affects. The V.35 termination resistor network is switched off when the receiver is disabled either by the decoder or receiver enable pin. The termination network is transparent when all other modes are selected. The V.35 receivers can operate over 10Mbps. To Inverting Input of Receiver V.11 TERMINATION MODE [0100] RIN [a] V.35 MODE rON = 20 rON = 1 51 rON = 1 124 51 To Non-Inverting Input of Receiver RIN [b] Figure 51. Simplified RIN Termination Circuit Receiver Enable and Output Only one receiver includes an enable line. The SCTEN input for the SCT receiver can enable or tri-state the output of the receiver. When the pin is at a logic "0", the receiver output is high impedance and any input termination internal connected is switched off. The inputs will be at approximately 10k during tri-state. SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 21 All receivers include a fail-safe feature that outputs a logic "1" when the receiver inputs are open. The differential receivers allocated for data and clock signals (RxD, RxC, and SCT) have advanced fail-safe that outputs a logic "1" when the inputs are either open, shorted, or terminated. Other discrete or integrated implementations require external pull-up and pulldown resistors to define the receiver output state. For single-ended V.28 receivers, there are internal 5k pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. The single-ended V.10 receivers produce a logic LOW ("0") on the output when the inputs are open. This is due to an internal pullup device connected to the input. The differential receivers have the same internal pull-up device on the non-inverting input which produces a logic HIGH ("1") at the receiver output, representing an "OFF" state to the HDLC controller. The three differential receivers when configured in V.35 mode (RxD, RxC & SCT) will also include fail-safe even when the internal termination resistor network is connected and the inputs are either shorted or floating. Decoder The SP505 has the ability to change the interface mode of the drivers or receivers via a 4-bit switch. The decoder for the drivers and receivers can be latched through a control pin. The control word can be latched either high or low to write the appropriate code into the SP505. The codes shown in Tables 1 and 2 are the only specified, valid modes for the SP505. Undefined codes may represent other interface modes not specified (consult the factory for more information). The drivers and receivers are controlled with the data bits labeled DEC3-DEC0. All of the drivers outputs and receiver outputs can be put into tri-state mode by writing 0000 to the driver decode switch. All internal termination networks are switched off during this mode. Individual tri-state capability is possible for all drivers through each driver's own enable control input. The SCT receiver also contains an individual enable input. When this control pin is disabled (logic "0"), the V.11 and V.35 input termination is deactivated. The 0000 decoder word will override the enable control line for the one receiver (SCT). The SP505 contains internal loopback capabilities for self-diagnostic tests. Loopback is enabled through the decoder. To initiate singleended mode loopback, the decoder word is 1010. To initiate differential mode loopback, the decoder word is 1011. The minimum transmission rates into the SP505 under loopback conditions are 120kbps for single-ended mode and 5Mbps for differential mode. The driver outputs are tristated and the receiver inputs are disabled during loopback. The receiver input impedance during loopback is approximately 10k. The SP505 is equipped with a latch control for the four (4) decoder bits. The latch control pin is pin 8 of the SP505. The latch control is active low, a logic low on pin 8 will latch the decoder signals. A logic "1" on pin 8 will force the latch to be transparent to the user. A pulse width of at least 30ns is required to latch the decoder for the next mode. The resultant output is typically 600ns after the latch control pin is toggled assuming that the decoder word is set. NET1/2 & TBR2 European Compliancy As with all of Sipex's previous multi-protocol serial transceiver ICs, the drivers and receivers have been designed to meet all the requirements to NET1/2. The SP505 is internally tested to all the NET1/2 physical layer testing parameters and the ITU Series V specifications. With the emergence of ETSI TBR2 (Technical Basis for Regulation) document now in place as an alternative for European compliancy, Sipex has tested the SP505 to TBR2 specifications to ensure "CE" approval for either testing method. The SP505 was externally tested by TUV Telecom Services, Division of TUV Rheinland, and passed both NET1/2 and TBR2 requirements. Test reports (NET2/052101/98 for NET1/2 and CTR2/ 05101/98 for TBR2) can be furnished upon request. Please note that although the SP505 adheres to NET1/2 testing; any complex or unusual configuration should be double-checked to ensure NET compliance. Consult factory for details. Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 22 SP505 Driver Mode Selection Pin Label DEC3 - DEC0 SD(a) SD(b) TR(a) TR(b) RS(a) RS(b) RL(a) RL(b) LL(a) LL(b) ST(a) ST(b) TT(a) TT(b) Mode: 0000 tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state RS232 0010 V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.35 1110 V.35- V.35+ V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.35- V.35+ V.35- V.35+ RS422 w/ Term. RS422 0101 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ RS449 1100 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.10 tri-state V.10 tri-state V.11- V.11+ V.11- V.11+ EIA530 1101 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.10 tri-state V.11- V.11+ V.11- V.11+ EIA-530A 1111 V.11- V.11+ V.10 tri-state V.11- V.11+ V.11- V.11+ V.10 tri-state V.11- V.11+ V.11- V.11+ V.36 0110 V.11- V.11+ V.10 tri-state V.10 tri-state V.10 tri-state V.10 tri-state V.11- V.11+ V.11- V.11+ 0100 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ Table 1. SP505 Driver Decoder Table SP505 Receiver Mode Selection Pin Label Mode: 0000 >10k to GND RS232 0010 V.28 V.35 1110 V.35- V.35+ V.35- V.35+ V.28 RS422 w/ Term. RS422 0101 RS449 1100 120 EIA530 1101 120 EIA-530A 1111 120 V.36 0110 120 120 120 DEC3 - DEC0 RD(a) RD(b) RT(a) RT(b) CS(a) CS(b) DM(a) DM(b) RR(a) RR(b) IC(a) IC(b) SCT(a) SCT(b) 0100 120 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.10 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.10 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.10 V.11- V.11+ V.11- V.11+ V.10 >10k to GND >10k to GND >10k to GND V.28 120 120 120 >10k to GND >10k to GND >10k to GND V.28 >10k to GND >10k to GND >10k to GND >10k to GND V.28 V.28 120 >10k to GND V.10 >10k to GND >10k to GND >10k to GND >10k to GND V.28 V.28 >10k to GND >10k to GND V.11- V.11+ V.10 >10k to GND 120 V.10 >10k to GND V.10 >10k to GND V.11- V.11+ >10k to GND >10k to GND >10k to GND >10k to GND V.28 V.28 >10k to GND V.35- V.35+ >10k to GND >10k to GND >10k to GND V.28 >10k to GND 120 >10k to GND 120 >10k to GND >12k to GND 120 V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ V.11- V.11+ Table 2. SP505 Receiver Decoder Table Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 23 1N5819 (SEE PINOUT FOR VCC PINS) 22F 22F 22F +5V 10F 25 VCC 27 26 30 28 31 22F VDD C1+ C1- C2+ C232 Charge Pump VSS A RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM (b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 RS-422 Mode Input Word DECODER LATCH B 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN 0 1 0 0 9 10 11 12 8 LATCH MODE X SP505 A -- Receiver Tri-State circuitry, V.11, & V.35 termination resistor circuitry (RxD, RxC & SCT). B -- Driver Tri-State circuitry & V.35 termination circuitry (TxD, TxC & ST). (SEE PINOUT ASSIGNMENTS FOR GROUND PINS) Figure 52. SP505 Typical Operating Circuit Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 24 MODE: RS-232 (V.28) DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 0 1 0 14 TxD RD(a) 70 RxD 1 61 SD(a) 2 SDEN 13 DTR RT(a) 37 58 TR(a) RxC 20 3 TREN CS(a) 66 CTS 80 16 RTS 54 RS(a) 4 RSEN DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 22 ST 42 ST(a) 23 STEN SCT(a) 76 SCT 79 SCTEN 7 6 TTEN 15 TxC 63 TT(a) RECEIVERS DRIVERS Figure 53. Mode Diagram -- RS-232 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 25 MODE: V.35 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 1 1 0 RD(a) 70 V.35 Ntwk V.35 Ntwk 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR V.35 Ntwk RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 58 TR(a) 3 TREN 16 RTS 54 RS(a) 4 RSEN DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 V.35 Ntwk 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC V.35 Ntwk V.35 Ntwk SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 54. Mode Diagram -- V.35 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 26 MODE: RS-422 [w/ termination] DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 1 0 0 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 120 120 120 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 55. Mode Diagram -- RS-422 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 27 MODE: RS-449 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 120 120 1 0 0 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 18 RLEN 24 LL 51 LL(a) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 120 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 56. Mode Diagram -- RS-449 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 28 MODE: RS-422 [no termination] DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 1 0 1 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 57. Mode Diagram -- RS-422 w/o termination Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 29 MODE: EIA-530 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 1 0 1 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 120 120 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 120 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 58. Mode Diagram -- EIA-530 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 30 MODE: EIA-530A DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 1 1 1 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 120 120 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 24 LL 51 LL(a) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 120 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 59. Mode Diagram -- EIA-530A Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 31 MODE: V.36 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 1 1 0 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 120 120 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 3 TREN 16 RTS 54 RS(a) 4 RSEN RxC 20 RT(b) 38 CS(a) 66 CTS 80 DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 120 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 60. Mode Diagram -- V.36 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 32 LOOPBACK MODE... The SP505 is equipped with two loopback modes. Single-ended loopback internally connects V.28 driver outputs to V.28 receiver inputs. The signal path is non-inverting and will support data rates up to 120kbps. The propagation delay times are as specified in the electrical specifications. To initiate a single-ended loopback, the code "1010" should be written to the driver decoder. Differential loopback is implemented by applying "1011" to the driver decoder. This internally connects V.11 driver MODE: Single-Ended Loopback DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 0 1 0 14 TxD RD(a) 70 RxD 1 61 SD(a) 2 SDEN 13 DTR RT(a) 37 58 TR(a) RxC 20 3 TREN CS(a) 66 CTS 80 16 RTS 54 RS(a) 4 RSEN DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 22 ST 42 ST(a) 23 STEN SCT(a) 76 SCT 79 SCTEN 7 6 TTEN 15 TxC 63 TT(a) outputs to V.11 receiver inputs. The signal path again is non-inverting; the differential loopback data rate can be at least 5Mbps. Under loopback conditions the receiver decoder is disabled. While the SP505 is in either singleended or differential loopback mode, the driver outputs are tri-stated and the receiver inputs are disabled. MODE: Differential Loopback DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 0 1 1 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS RECEIVERS DRIVERS Mode Loopback DEC=1010 DEC=1011 Driver Output non-inverting tri-state tri-state inverting tri-state tri-state Receiver Input non-inverting inverting Driver Receiver Input Output active active >10K to GND >10K to GND active >10K to GND >10K to GND active Power down VCC=VDD=VSS=0V tri-state tri-state tri-state tri-state clamped >10K to GND >10K to GND inactive at 0.6V >10K to GND >10K to GND inactive tri-state Tri-state DEC=0000 Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 33 PACKAGE: 80 PIN MQFP D D1 D2 PIN 1 c 0.30" RAD. TYP. 0.20" RAD. TYP. C L E1 E E2 0 MIN. 5-16 0-7 5-16 C L L L1 A2 b e A1 A Seating Plane DIMENSIONS Minimum/Maximum (mm) SYMBOL A A1 A2 b D D1 D2 E E1 E2 e N 80-PIN MQFP JEDEC MS-22 (BEC) Variation MIN 0.00 1.80 0.22 17.20 BSC 14.00 BSC 12.35 REF 17.20 BSC 14.00 BSC 12.35 REF 0.65 BSC 80 2.00 NOM MAX 2.45 0.25 2.20 0.40 COMMON DIMENTIONS SYMBL MIN c L L1 0.11 0.73 0.88 NOM MAX 23.00 1.03 1.60 BASIC 80 PIN MQFP (MS-022 BC) Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 34 PACKAGE: 80 PIN LQFP D D1 0.2 RAD MAX. c 0.08 RAD MIN. PIN 1 11 - 13 0 Min C L E1 E 0-7 11 - 13 L L1 C L A2 b DIMENSIONS Minimum/Maximum (mm) SYMBOL A A1 A2 b D D1 e E E1 N 0.05 1.35 0.22 1.40 0.32 A e 80-PIN LQFP JEDEC MS-026 (BEC) Variation MIN NOM MAX 1.60 0.15 1.45 0.38 A1 Seating Plane COMMON DIMENTIONS SYMBL MIN c L L1 0.11 0.45 0.60 NOM MAX 23.00 0.75 1.00 BASIC 16.00 BSC 14.00 BSC 0.65 BSC 16.00 BSC 14.00 BSC 80 80 PIN LQFP Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 35 ORDERING INFORMATION Model Temperature Range Package Types SP505ACF ........................................................................ 0C to +70C ...................................................... 80-pin JEDEC (BE-2 Outline) MQFP SP505BCF ........................................................................ 0C to +70C ...................................................... 80-pin JEDEC (BE-2 Outline) MQFP SP505ACM ....................................................................... 0C to +70C ....................................................... 80-pin JEDEC (BE-2 Outline) LQFP SP505BCM ....................................................................... 0C to +70C ....................................................... 80-pin JEDEC (BE-2 Outline) LQFP Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Rev. 7/9/03 SP505 Multi-Mode Serial Transceiver (c) Copyright 2003 Sipex Corporation 36 |
Price & Availability of SP505AB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |